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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-08-29T00:12:28Z
Would you like to attempt adding an option, say -trace-underscore, yourself?
Search for "Leading Underscore" and the next 3 lines in V3Trace.cpp. Then add a accessor to V3Option.h and parse it in V3Option.cpp, and document in bin/verilator. The options are in alphabetical order.
Author Name: Jason McMullan (@ezrec)
Original Redmine Issue: 280 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
I'm working with an existing (large) design that has a common idiom
of using an underscore ('_') prefix for wires/regs that are
active low.
Current head-of-line Verilator does not emit these signals in the
VCD trace, but does emit all other signals.
Is there an option to set (or a patch I can apply) to permit
Verilator to trace and dump signals that start with an underscore?
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