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Verilog preprocessor does not expand macros in argument #283
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Original Redmine Comment Updating since the code segment does not show up as expected: Trying to expand the following macro definition:
I would expect the last As the macro is expanded, the arguments are fully expanded before the next expansion, I would expect the following steps:
|
Original Redmine Comment Unfortunately the specification doesn't clearly specify the order of expansion, so the results depends on the simulator. |
Original Redmine Comment Misspoke above, the order of expansion is specified, just not when `` is done during expansion. |
Original Redmine Comment First, I did some research, and only 3 of four simulators surveyed support this ordering. If you want to be maximally compliant, you may not want to do that. However, majority rules. I further discovered that the majority believes:
which is amazing, as I just wrote a paper that discovered a ton of odd stuff, but missed this! Anyhow, fixed in git, for 3.303. |
Original Redmine Comment In 3.303 |
Author Name: Usha Priyadharshini
Original Redmine Issue: 283 from https://www.veripool.org
Original Date: 2010-09-16
Original Assignee: Wilson Snyder (@wsnyder)
Hi,
I am trying to expand the following macro definition:
define FRAME_TYPE sonet
define JOIN(__arg1, __arg2) __arg1``__arg2define XACTION
JOIN(`FRAME_TYPE, _frame)`XACTION
I would expect the last
XACTION call expanding to sonet_frame. However output of preprocessor shows
FRAME_TYPE_frame. Parsing this in VCS produces the expected output: sonet_frameAs the macro is expanded, the arguments are fully expanded before the next expansion, I would expect the following steps:
XACTION
JOIN(FRAME_TYPE, _frame)
JOIN(cxtf, _frame)cxtf``_frame
cxtf_frame
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