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Identation of classes inside package in SystemVerilog #286

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veripoolbot opened this issue Sep 27, 2010 · 0 comments
Closed

Identation of classes inside package in SystemVerilog #286

veripoolbot opened this issue Sep 27, 2010 · 0 comments

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Author Name: Pierre-David Pfister
Original Redmine Issue: 286 from https://www.veripool.org


Hi,
Classes are not indented when declared in a package.

package toto;
class titi;
endclass
endpackage

Should rather be, in my opinion:

package toto;
class titi;
endclass
endpackage

Thanks,
Pierre

I'm using version 639 of Verilog mode.

wsnyder pushed a commit that referenced this issue May 22, 2022
…inside packages (#286) (#1769).

* verilog-mode.el (verilog-defun-no-class-re, verilog-do-indent)
(verilog-end-defun-no-class-re, verilog-indent-class-inside-pkg)
(verilog-mode, verilog-submit-bug-report)
(verilog-zero-indent-no-class-re): Add
`verilog-indent-class-inside-pkg' and fix indentation of classes
inside packages (#286) (#1769).  Reported by Gonzalo Larumbe.

Signed-off-by: Gonzalo Larumbe <gonzalomlarumbe@gmail.com>
@wsnyder wsnyder closed this as completed May 22, 2022
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