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incorrect source file name in error message after include #289

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veripoolbot opened this issue Sep 28, 2010 · 2 comments
Closed

incorrect source file name in error message after include #289

veripoolbot opened this issue Sep 28, 2010 · 2 comments
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area: parser Issue involves SystemVerilog parsing resolution: fixed Closed; fixed

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Author Name: Brad Parker (@lisper)
Original Redmine Issue: 289 from https://www.veripool.org
Original Date: 2010-09-28
Original Assignee: Wilson Snyder (@wsnyder)

I have some, ahem, top level .v files which include other .v files

I noticed that if there is a syntax error in one of the included .v files,
verilator gets confused about which source file the error is in. The line
number appears correct, however.

I made a simple example project which show this (included in the tar file)

I'll try and track it down at some point and post diffs.

verilator reports it's version as:
Verilator 3.803 2010/07/10 rev verilator_3_802-9-g5e4ca4b
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-09-28T13:34:13Z

If you run with -E, it'll show the preprocessed source, which shows the problem.

I'm pretty sure that's due to a recent change that was pulled from Verilog-Perl... yup.... Fixed in git.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-10-26T14:23:14Z

In 3.304.

@veripoolbot veripoolbot added area: parser Issue involves SystemVerilog parsing resolution: fixed Closed; fixed labels Dec 22, 2019
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