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Author Name: Pierre-David Pfister
Original Redmine Issue: 290 from https://www.veripool.org
Original Date: 2010-09-30
Original Assignee: Michael McNamara
Hi,
The Verilog-mode adds an extra indentation after import of DPI-C function:
module toto (input logic dummy);
import "DPI-C" pure function real fabs (input real a);
logic a; // wrong indentation
endmodule // wrong indentation
Thanks,
Pierre
The text was updated successfully, but these errors were encountered:
Author Name: Pierre-David Pfister
Original Redmine Issue: 290 from https://www.veripool.org
Original Date: 2010-09-30
Original Assignee: Michael McNamara
Hi,
The Verilog-mode adds an extra indentation after import of DPI-C function:
Thanks,
Pierre
The text was updated successfully, but these errors were encountered: