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Verilator crashes on 'output wire foo = 0' in portlist #291

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veripoolbot opened this issue Oct 4, 2010 · 4 comments
Closed

Verilator crashes on 'output wire foo = 0' in portlist #291

veripoolbot opened this issue Oct 4, 2010 · 4 comments
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area: parser Issue involves SystemVerilog parsing resolution: fixed Closed; fixed

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Author Name: Joshua Wise
Original Redmine Issue: 291 from https://www.veripool.org
Original Date: 2010-10-04
Original Assignee: Wilson Snyder (@wsnyder)


If I do something very unusual in a stub module (very minimized test case):

module FSABArbiterFIFO(output wire inp_credit = 0);

endmodule

then Verilator crashes in an exciting fashion:

joshua@escape:~/school/18-545/virtexsquared/runs/test/sim/breakage$ gdb --args verilator_bin_dbg --debug  -Irtl --cc FSABArbiterFIFO.v
GNU gdb 6.3.50-20050815 (Apple version gdb-1344) (Fri Jul  3 01:19:56 UTC 2009)
Copyright 2004 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB.  Type "show warranty" for details.
This GDB was configured as "x86_64-apple-darwin"...Reading symbols for shared libraries ... done

(gdb) run
Starting program: /usr/local/bin/verilator_bin_dbg --debug -Irtl --cc FSABArbiterFIFO.v
Reading symbols for shared libraries ++. done
Starting Verilator 3.804 2010/07/10 rev verilator_3_803-9-g16b0c8d
- V3Options.cpp:329:  export SYSTEMC_ARCH=linux # From sysname 'darwin'
- V3File.cpp:200:        --check-times failed: different command line
- V3GraphTest.cpp:356:test:
- V3ParseImp.cpp:95:  parseFile: FSABArbiterFIFO
  Preprocessing FSABArbiterFIFO.v
- V3PreShell.cpp:105:     Reading FSABArbiterFIFO.v
- V3ParseImp.cpp:141: Lexing FSABArbiterFIFO.v

Program received signal EXC_BAD_ACCESS, Could not access memory.
Reason: KERN_INVALID_ADDRESS at address: 0x0000000000000000
0x000000010001ce86 in yyparse () at verilog.y:833
833     verilog.y: No such file or directory.
         in verilog.y
(gdb) bt
#0  0x000000010001ce86 in yyparse () at verilog.y:833
#1  0x0000000100031f79 in V3ParseImp::bisonParse (this=0x100802070) at verilog.y:3039
#2  0x00000001000139f9 in V3ParseImp::lexFile (this=0x100802070, modname=@0x7fff5fbfe650) at ../V3ParseImp.cpp:148
#3  0x000000010001417e in V3ParseImp::parseFile (this=0x100802070, fileline=0x100802750, modfilename=@0x7fff5fbfe650, inLibrary=false) at ../V3ParseImp.cpp:135
#4  0x00000001000141ed in V3Parse::parseFile (this=0x7fff5fbfe680, fileline=0x100802750, modname=@0x7fff5fbfe650, inLibrary=false) at ../V3ParseImp.cpp:161
#5  0x0000000100075187 in V3Global::readFiles (this=0x1003e15e0) at ../Verilator.cpp:109
#6  0x0000000100075f5f in main (argc=5, argv=0x7fff5fbfea08, env=0x7fff5fbfea38) at ../Verilator.cpp:603
(gdb)

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-10-04T11:53:02Z


Off-by-one error!

Fixed in git for 3.805+.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-10-04T11:53:45Z


BTW that's SystemVerilog syntax, if you weren't aware.

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Original Redmine Comment
Author Name: Joshua Wise
Original Date: 2010-10-04T11:57:53Z


Wilson Snyder wrote:

BTW that's SystemVerilog syntax, if you weren't aware.

I suspect I'm going to have an "interesting time" when we finish the I/O bits for real hardware and run this through XST.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-11-03T01:26:17Z


In 3.805.

@veripoolbot veripoolbot added area: parser Issue involves SystemVerilog parsing resolution: fixed Closed; fixed labels Dec 22, 2019
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