(preprocessor) define propagates across files #306
Comments
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Original Redmine Comment Are you comparing this against another simulator? This is unfortunately the way it must work, it wouldn't have been my choice :) `defines have effect across the entire compilation unit, per spec, and many designs require that. If you don't want this, use `undefineall at the end of your modules. I might be convinced to make each file on the command line a separate compilation unit, but you need to be sure this is what you really want, as few other tools support that so it might not make for a portable environment. |
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Original Redmine Comment Thanks a lot for the explanation! (the chip is simulated with ModelSim with VHDL on top level Thanks, |
veripoolbot
added
area: parser
* Retrieve constant sizes from UHDM; create AstConsts instead of V3Numbers * Enable ConstSizes test * Fix unsized constants exceeding 64 bits * Bump Surelog; handle Surelog's default constant size of 64 bits
* Retrieve constant sizes from UHDM; create AstConsts instead of V3Numbers * Enable ConstSizes test * Fix unsized constants exceeding 64 bits * Bump Surelog; handle Surelog's default constant size of 64 bits
Author Name: Pawel Jewstafjew
Original Redmine Issue: 306 from https://www.veripool.org
Original Date: 2010-12-02
Original Assignee: Wilson Snyder (@wsnyder)
Verilator version: 3.805 (and, at least 3.803)
preprocessor 'define should be cleared at the scope
instead it is still active is all the files loaded afterwards
For example, two modules are instantiated for top.v
mod_a i_a ();
mod_b i_b ();
in mod_a.v:
define MOD_A_DEFdefine MY_DEF Ain mod_b.v:
define MOD_B_DEFdefine MY_DEF Bifdef MOD_A_DEF this should not be defined here !!!endifVerilator output:
%Warning-REDEFMACRO: mod_b.v:6: Redefining existing define: MY_DEF, with different value: B
%Warning-REDEFMACRO: Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message.
%Warning-REDEFMACRO: mod_a.v:13: Previous definition is here, with value: A
%Error: mod_b.v:8: Unsupported: SystemVerilog 2005 reserved word not implemented:
this
%Error: mod_b.v:8: syntax error, unexpected "not", expecting "IDENTIFIER"
<-- preprocessor definitions from mod_a.v are visible in mod_b.v
verilator invocation:
verilator -cc top.v
example files are attached
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