Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Possible problem with ->verilog_text #31

Closed
veripoolbot opened this issue Sep 15, 2008 · 3 comments
Closed

Possible problem with ->verilog_text #31

veripoolbot opened this issue Sep 15, 2008 · 3 comments
Assignees

Comments

@veripoolbot
Copy link
Collaborator


Author Name: Jeff Short
Original Redmine Issue: 31 from https://www.veripool.org
Original Date: 2008-09-15
Original Assignee: Wilson Snyder (@wsnyder)


When I call $nl->verilog_text where $nl is a Verilog::Netlist object, the value property on a net seems to be dropped.

Example:
wire PWROK = VDD & ~VSS;

->dump on PWROK returns:
Net:PWROK Type:wire Array: Value:VDD&~VSS

However the ->verilog_text only shows:
wire PWROK;

It looks like I am using version 3.040 of your code.

Jeff Short

@veripoolbot
Copy link
Collaborator Author


Original Redmine Comment
Author Name: Jeff Short
Original Date: 2008-09-16T22:55:08Z


I was able to fix the output by doing the following in Net.pm :
sub verilog_text {
my $self = shift;
my @out;
foreach my $decl ($self->_decls) {
push @out, $decl;
push @out, " [".$self->msb.":".$self->lsb."]" if defined $self->msb;
push @out, " ".$self->name;
push @out, " ".$self->array if $self->array;
push @out, " = ".$self->value if defined $self->value && $self->value ne '';
push @out, ";";
}
return (wantarray ? @out : join('',@out));
}

Just added one new line to deal with value. Not sure this is 100% correct but it works in my case anyway. Let me know what you think.

Jeff

@veripoolbot
Copy link
Collaborator Author


Original Redmine Comment
Author Name: Jeff Short
Original Date: 2008-09-16T22:56:16Z


Well posting the text in this window didn't work well. Trying as attachment.

Jeff

@veripoolbot
Copy link
Collaborator Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2008-09-17T14:03:00Z


Thanks for the patch, that makes sense. I've pushed it to the GIT version and it'll be in the next release.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

2 participants