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Scope resolution operator not supported in port declarations #315

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veripoolbot opened this issue Jan 11, 2011 · 2 comments
Closed

Scope resolution operator not supported in port declarations #315

veripoolbot opened this issue Jan 11, 2011 · 2 comments

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Author Name: Divyanand Kutagulla
Original Redmine Issue: 315 from https://www.veripool.org
Original Date: 2011-01-11

Given port declaration verilog code:
input UPF::supply_net_type vddmp;

Verilog::Parser errors out on the scope-resolution operator
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-01-11T20:45:06Z

Works for me, perhaps you forgot to include the code that declares UPF?

package imp_test_pkg;
typedef logic [7:0] byte_t;
endpackage
module #�;
input imp_test_pkg::byte_t i;
endmodule

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-01-12T00:00:36Z

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