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Port callback incorrectly setting up direction for ports of user defined types #316

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veripoolbot opened this issue Jan 11, 2011 · 2 comments
Closed

Port callback incorrectly setting up direction for ports of user defined types #316

veripoolbot opened this issue Jan 11, 2011 · 2 comments
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Author Name: Divyanand Kutagulla
Original Redmine Issue: 316 from https://www.veripool.org
Original Date: 2011-01-11
Original Assignee: Wilson Snyder (@wsnyder)

Verilog_parser uses the port callback to process verilog port declarations inside module scope:
input supply_net_type vddmp;

But inside the port callback the direction attribute is incorrectly set to interface when it should be set to input

Port declarations:
input logic vddmp;
are handled correctly; The port callback correctly sets the direction to input.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-01-11T21:52:43Z

For

module t;
typedef int supply_net_t;
input int i;
input supply_net_t #�;
endmodule

I get the following for the callback

verilog/parser_sv.v:352: MODULE 'module' 't' undef '0'
verilog/parser_sv.v:353: VAR 'typedef' 'supply_net_t' 'module' '' 'int' '' ''
verilog/parser_sv.v:354: VAR 'port' 'i' 'module' '' 'int' '' ''
verilog/parser_sv.v:354: PORT 'i' 'module' 'input' 'int' '' '0'
verilog/parser_sv.v:356: VAR 'port' '#�' 'module' '' 'supply_net_t' '' ''
verilog/parser_sv.v:356: PORT '#�' 'module' 'input' 'supply_net_t' '' '0'
verilog/parser_sv.v:357: ENDMODULE 'endmodule'

which looks correct; can you see the issue above, or send an example?

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-01-12T00:01:00Z

User's issue

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