Author Name: Guy-Armand Kamendje
Original Redmine Issue: 32 from https://www.veripool.org
Original Date: 2008-09-20
Original Assignee: Wilson Snyder (@wsnyder)

I also noticed that Verilator 3.665 will accept modules with incomplete IO port list. I am not very familiar with the Verilog standard but I noticed that synthesis tool will rather flag a severe error in such cases. What I mean is the following:

module foo(clk, reset );
input clk; // <== clock signal
input reset; // <== reset signal
input work_in; // <==
endmodule

Omitting to include the signal work_in in the port list does not result in a error. Is there a compiler option that has to be set in order to catch these cases?