Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-03-08T01:48:26Z

The existing ones should mostly work with SystemVerilog as-is; if there's something specific missing, let us know. Be sure your verilog-typedef-regexp is set correctly.

Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2011-03-08T01:59:57Z

Yes, I agree: existing AUTOs work fine with SystemVerilog.

The reason I am wondering is that we are starting a new project and decided to use SystemVerilog "logic" type instead of Verilog "wire"/"reg". However, AUTOs are still very useful in many cases, e.g. testbenches, but they don't generate "logic" declarations. So, it is more a question about consistency of coding.

Also, I think AUTOLOGIC would substitute all 3 existing macros AUTOWIRE/AUTOREG/AUTOREGINPUT, one would use AUTOLOGIC instead of AUTOWIRE/AUTOREG or AUTOWIRE/AUTOREGINPUT.

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-04-12T19:33:42Z

Finally added AUTOLOGIC, which is like AUTOWIRE. It doesn't combine AUTOREG yet, but you can set verilog-auto-wire-type then use AUTOREG, and AUTOREG will use "logic". Please file a bug if you have any problems.

Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2011-04-12T21:29:09Z

It looks like version 676 with AUTOLOGIC has new bugs (as well as old ones):

1. AUTOOUTPUT does not generate outputs:

   /AUTOOUTPUT/
   // Beginning of automatic outputs (from unused autoinst outputs)
   logic any_sign_match, // From ...
   logic any_zero_sign, // From ...

2. AUTOINPUT does not generate inputs:

   /AUTOINPUT/
   // Beginning of automatic inputs (from unused autoinst inputs)
   logic clk, // To u_seq_ff of r_flop.v, ...

3. AUTOOUTPUT/AUTOINPUT/AUTOLOGIC/AUTOREG do not generate anything for signals defined in submodules using typedefs.

4. AUTOOUTPUT/AUTOINPUT/AUTOLOGIC/AUTOREG do not seem to understand generate statements, e.g.:

   /AUTOINPUT/
   // Beginning of automatic inputs (from unused autoinst inputs)
   ...
   logic [WIDTH-1:0] write_data_in // To ...
   // End of automatics

   // Bring wide inputs sequentially
   genvar i;
   generate
   for( i=0; i < SEQ_RATIO; i++ ) begin : SEQ_REG e_flop #(DRAM_WIDTH/SEQ_RATIO) u_dram_data_in_ff( .en(seq_d1[i]),
   .i(dram_data_seq_in),
   .o(dram_data_in[(DRAM_WIDTH/SEQ_RATIO)*i +: DRAM_WIDTH/SEQ_RATIO]),
   .*);
   e_flop #(WIDTH/SEQ_RATIO) u_write_data_in_ff( .en(seq_d1[i]), .i(write_data_seq_in), .o(*write_data_in*[(WIDTH/SEQ_RATIO)i +:
   WIDTH/`SEQ_RATIO]),
   .);
   end
   endgenerate

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-04-13T12:27:27Z

1. Fixed.

2. Fixed.

3. I don't think this is related to the change. I suspect you need to set verilog-typedef-regexp

4. I don't think this is related to the change. I think you need // Outputs before your signal names
   in the instantiation. See the FAQ, http://www.veripool.org/wiki/verilog-mode/Faq#Why-doesnt-AUTOWIRE-include-the-outputs-from-a-submodule

Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2011-04-14T17:48:05Z

3 and 3: I was confused - the problem is not with typedefs or generate statements but with parameterizable instantiations, which are not supported by AUTOs as far as I understand.

After adding // Outputs I got broken code like:

/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)                                                                                                       
logic                buf_to_dram_wb_ind_d1;  // From u_buf_to_dram_wb_ind_ff of flop.v                                                                                             
logic [(DRAM_WIDTH/`SEQ_RATIO)*i +:
                                                                         DRAM_WIDTH/`SEQ_RATIO] dram_data_in;// From u_dram_data_in_ff of e_flop.v                       
// End of automatics


flop #($clog2(WB_DEPTH)) u_buf_to_dram_wb_ind_ff( // Outputs                                                                                                                       
                                                  .o(buf_to_dram_wb_ind_d1),
                                                  // Inputs                                                                                                                        
                                                  .i(buf_to_dram_wb_ind),
                                                  .*);

// Bring wide inputs sequentially                                                                                                                                                  
genvar                 i;
generate
   for( i=0; i < `SEQ_RATIO; i++ ) begin : SEQ_REG
      e_flop #(DRAM_WIDTH/`SEQ_RATIO) u_dram_data_in_ff( // Outputs                                                                                                                
                                                         .o(dram_data_in[(DRAM_WIDTH/`SEQ_RATIO)*i +:
                                                                         DRAM_WIDTH/`SEQ_RATIO]),
                                                         // Inputs                                                                                                                 
                                                         .en(seq_d1[i]),
                                                         .i(dram_data_seq_in),
                                                         .*);

Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2011-04-14T18:31:07Z

One more thing: in some cases AUTOOUTPUT/AUTOINPUT drop logic in declaration:

 /*AUTOOUTPUT*/
 // Beginning of automatic outputs (from unused autoinst outputs)
 output mc_addr_t    dram_addr_out,          // From ...
 output              dram_burstbegin_out,    // From ...
 output [DRAM_WIDTH-1:0] dram_data_out,      // From ...

which causes errors in modelsim:

** Error: ..._mc_channel.v(34): Net type of 'dram_data_out' must be explicitly declared (`default_nettype is "none").

Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2011-04-14T18:44:14Z

Also, in another case AUTOOUTPUT generates declaration for bus that is already declared inside the module manually:

/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output mc_addr_t     dram_addr_out,          // From ...
output logic         dram_burstbegin_out,    // From ...
output logic [DRAM_WIDTH-1:0] *dram_data_out*, // From ...
// End of automatics

);

logic [`SEQ_RATIO-1:0] seq_d1;
logic [WIDTH-1:0]      write_data_in;

logic [DRAM_WIDTH-1:0] *dram_data_out*;