Author Name: Alex Solomatnikov
Original Redmine Issue: 327 from https://www.veripool.org
Original Date: 2011-02-23
Original Assignee: Wilson Snyder (@wsnyder)

The following code:

typedef enum [3:0] { NOP = 0 } req_t;

module arbiter
(
output wire valid_out,
output req_t type_out,
input wire valid_in,
input req_t type_in
);

wire [$bits(req_t):0] internal_type = { 1'b0, type_in };

endmodule // arbiter

results in error:

verilator --cc typedef_bug.v
%Error: typedef_bug.v:11: syntax error, unexpected TYPE-IDENTIFIER
%Error: Exiting due to 1 warning(s)
%Error: Command Failed verilator_bin --cc typedef_bug.v

This is supposed to work according to SystemVerilog 3.1a LRM which has the following example:

typedef struct {
logic valid;
bit [8:1] data;
} MyType;

typedef bit[$bits(MyType):1] MyBits;
MyBits b;