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port named 'ref' #328

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veripoolbot opened this issue Mar 2, 2011 · 2 comments
Closed

port named 'ref' #328

veripoolbot opened this issue Mar 2, 2011 · 2 comments

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Author Name: Daniel Schoch
Original Redmine Issue: 328 from https://www.veripool.org
Original Date: 2011-03-02

The parser complains about module ports named 'ref'. I assume that's a bug, however I'm not that familiar with verilog so I might be wrong.

Following line wont parse, aborting with syntax error because of port named 'ref'. Renaming 'ref' to something else works fine.

module rtl_spislave(so_xoe, zwindow , frame_set , bus_wr , bus_rd , xss , sclk , si ,
     spi_3wire , xrst , si_xoe , si_out , so , bus_dout , bus_a , bus_din , inc, ref );
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-03-02T13:31:52Z

"ref" is a SystemVerilog keyword. You should fix the code, or use the --language (or Verilog::Language::language_standard) option.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-03-02T13:34:28Z

BTW, there's more info on the general keyword problem in the paper here in section 2.1:

http://www.veripool.org/papers/TenIPEdits_SNUGBos07_paper.pdf

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