Adding feature for case modifiers in SV #33
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Original Redmine Comment Love getting patches! You did all of the right things. I just made a few trivial changes (the yNAME should match keyword NAME). Also looking at the spec there's a "unique if" construct so I threw that in too. All checked into git, and will be in the next release. As for the testing, I generally add it to verilog/parser_bugs.v. The tests will still fail, because there's different modules or filenames. So run the test that fails with "t/sigparser.t". A "diff test_dir/35.dmp t/35_sigparser.out" will show the differences (generally trivial). If they make sense then "cp test_dir/35.dmp t/35_sigparser.out" to make the tests now pass. |
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Author Name: Nicky Ayoub
Original Redmine Issue: 33 from https://www.veripool.org
Original Date: 2008-10-10
Original Assignee: Wilson Snyder (@wsnyder)
A buddy here is trying to use the sigparser on some SV code that uses 'unique case' modifiers.
I have modified the lexer and grammar to support unique and priority in a very simple manner.
The patch is attached.
I really could not figure out how to test this change properly. I added 'unique'
to case statement in example.v and noticed that it is observed during make test.
If I replace it with a generic keyword like 'rand' then the 36_sigmany test fails. This leads me to believe that the grammar is being validated properly because I don't see an error in this test when using 'unique'.
I am not as familiar with the design of the software to know if I have broken any other part of the parser.
Nor am I able to estimate the impact of such a small change.
So, I would really appreciate some guidance.
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