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Identation after always* construct inside named block #330

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veripoolbot opened this issue Mar 8, 2011 · 3 comments
Closed

Identation after always* construct inside named block #330

veripoolbot opened this issue Mar 8, 2011 · 3 comments
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indents wontfix

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@veripoolbot
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Author Name: Pierre-David Pfister
Original Redmine Issue: 330 from https://www.veripool.org

Hi,

It looks like indentation is wrong after the first always_ff (I think this is also true for other types of always) inside a named block (I'm using version 665). E.g.:

module testcase;
  begin : block
     logic s1, s2;
     wire w1 = '1;
     wire w2 = '0;
     always_ff @(clk) s1 <= w1;
  always_ff @(clk) s2 <= s1; // wrong indentation
end // wrong indentation
endmodule

Thanks,
Pierre
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Original Redmine Comment
Author Name: Pierre-David Pfister
Original Date: 2011-03-08T14:15:05Z

This is still true in 667, Pierre.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-03-09T02:59:16Z

Not that we shouldn't necessarily indent them, but "bare" begin/end blocks are a Verilog 2001 feature that were deprecated in SystemVerilog 2005.
Note if you throw it in a "generate"/"endgenerate" it works correctly.

Anyhow, up to Mac.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-11-19T13:11:39Z

Given bare end blocks are no longer standard, and there was not a patch, closing due to age.

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