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Author Name: Alex Solomatnikov
Original Redmine Issue: 335 from https://www.veripool.org
Original Date: 2011-03-16
Original Assignee: Wilson Snyder (@wsnyder)
Author Name: Alex Solomatnikov
Original Redmine Issue: 335 from https://www.veripool.org
Original Date: 2011-03-16
Original Assignee: Wilson Snyder (@wsnyder)
Example:
define MC_WIDTH 32 typedef logic [
MC_WIDTH-1:0] mc_t;module t( output mc_t o,
input mc_t i );
always_comb begin
o = mc_t'(1);
end
endmodule // t
Modelsim compiles just fine but verilator does not:
%Error: tmp.v:8: syntax error, unexpected TYPE-IDENTIFIER
%Error: Exiting due to 1 warning(s)
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