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type casting does not work #335

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veripoolbot opened this issue Mar 16, 2011 · 3 comments
Closed

type casting does not work #335

veripoolbot opened this issue Mar 16, 2011 · 3 comments
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Alex Solomatnikov
Original Redmine Issue: 335 from https://www.veripool.org
Original Date: 2011-03-16
Original Assignee: Wilson Snyder (@wsnyder)


Example:

define MC_WIDTH 32 typedef logic [MC_WIDTH-1:0] mc_t;

module t( output mc_t o,
input mc_t i );

always_comb begin
o = mc_t'(1);
end

endmodule // t

Modelsim compiles just fine but verilator does not:

%Error: tmp.v:8: syntax error, unexpected TYPE-IDENTIFIER
%Error: Exiting due to 1 warning(s)

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-03-18T02:27:15Z


Fixed in git for 3.812.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-03-18T02:27:55Z


BTW only simple scalar types are supported, no arrays etc. I suspect there will be later improvements needed here.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-04-06T11:41:18Z


In 3.812.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
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Labels
resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
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