You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Jacky Ma asked how to support naming conventions that add i_ for inputs of a block, and o_ for outputs of a block when using AUTOINST. The problem is that a signal name may need to change when the submodule's inputs are no longer inputs/outputs on the upper level.
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-05-10T06:38:19Z
First, I'd suggest that naming conventions that change the signal name as it crosses the hiearchy aren't recommended. This convention is also going to cause great difficulty when moving towards SystemVerilog interfaces.
That out of the way, make a special function in your site's .emacs file as follows:
Author Name: Wilson Snyder (@wsnyder)
Original Redmine Message: 516 from https://www.veripool.org
Jacky Ma asked how to support naming conventions that add i_ for inputs of a block, and o_ for outputs of a block when using AUTOINST. The problem is that a signal name may need to change when the submodule's inputs are no longer inputs/outputs on the upper level.
Here's an example
The text was updated successfully, but these errors were encountered: