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Width mismatch warnings #350

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veripoolbot opened this issue May 12, 2011 · 2 comments
Closed

Width mismatch warnings #350

veripoolbot opened this issue May 12, 2011 · 2 comments
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area: configure/compiling Issue involves configuring or compilating Verilator itself resolution: wontfix Closed; work won't continue on an issue or pull request

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Author Name: Amin Firoozshahian
Original Redmine Issue: 350 from https://www.veripool.org

It seems that when assigning constant expressions to a signal, Verilator expects the LSH to be as wide as the widest parameter on the RHS, rather than the result of the expression. For example, when compiling the following code:


`define NUM  32

module test
  (output logic [4:0] counter,
    input  logic       clk,
    input  logic       rst);

    always_ff @(posedge clk) begin
       if (rst)
         counter <= `NUM - 1;
       else
         counter <= counter - 1;
    end
endmodule // test

gets the following warning:

%Warning-WIDTH: test.v:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 or 6 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to 1 warning(s)
%Error: Command Failed verilator_bin --cc test.v --top-module test

This is while `NUM-1 fits exactly in the 5 bits provided by the LHS signal.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-05-12T17:18:49Z

True enough.

By the verilog rules, the expression "32 - 1" has width 32, which is what verilator correctly reports.

It's allowance of the width 5 is an attempt to reduce false warnings, but at the time the widths are resolved it can't know the expression will later resolve to a smaller width (because expression eval itself depends on width determination!) The best it can do for now is use the 5.

Sorry

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Original Redmine Comment
Author Name: Nathan Clarke
Original Date: 2016-11-10T08:14:59Z

I know this is an old issue, but I recently encountered this same problem using Verilator to get my RTL lint clean, and I managed to find a simple work-around using a localparam:

 localparam NUM_M1 = `NUM - 1;

 always_ff @(posedge clk) begin
     if (rst)
         counter <= NUM_M1[4:0];
     else
         counter <= counter - 1;
 end

Note that Verilator will treat NUM_M1 as having a width of either 32 or 5, so it is necessary to restrict the range to [4:0] when assigning to counter.

@veripoolbot veripoolbot added area: configure/compiling Issue involves configuring or compilating Verilator itself resolution: wontfix Closed; work won't continue on an issue or pull request labels Dec 22, 2019
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area: configure/compiling Issue involves configuring or compilating Verilator itself resolution: wontfix Closed; work won't continue on an issue or pull request
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