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Support '{...} #355
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Original Redmine Comment '{ is a system verilog feature I thought wouldn't really be needed until structures were supported, but I see how this can be useful. I'll look at adding it. Meanwhile you can just assign temp_array[0] = id0; |
Original Redmine Comment Yes, there is an obvious workaround. However, it requires a lot of meaningless extra code: I added 30 lines just because of 1 instantiation, which itself requires only 11 lines. |
Original Redmine Comment See #� for the parameter need for this. |
Original Redmine Comment Another example:
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Original Redmine Comment Hi, This feature is now called "Assignment patterns". In addition to arrays and structures it can be used on 1D vectors. The next example can be used to test the the feature applied to 1D vectors: Regards, Iztok Jeras |
Original Redmine Comment The structure version of '{} is in git towards 3.841. Hope to get to array '{} shortly. |
Original Redmine Comment '{} to arrays is in git towards 3.857. |
Original Redmine Comment In 3.860. |
Author Name: Alex Solomatnikov
Original Redmine Issue: 355 from https://www.veripool.org
Original Date: 2011-05-20
It turns out that the correct version of RTL from #� requires '{...} which is not supported by Verilator (other simulation and synthesis tools support it):
%Error: ..._control.v:422: syntax error, unexpected "'{", expecting TYPE-IDENTIFIER
Here is an example from IEEE 1800-2005 doc:
Array literals are syntactically similar to C initializers, but with the replicate operator ({{}} ) allowed.
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