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Support '{...} #355

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veripoolbot opened this issue May 20, 2011 · 8 comments
Closed

Support '{...} #355

veripoolbot opened this issue May 20, 2011 · 8 comments
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Alex Solomatnikov
Original Redmine Issue: 355 from https://www.veripool.org
Original Date: 2011-05-20


It turns out that the correct version of RTL from #� requires '{...} which is not supported by Verilator (other simulation and synthesis tools support it):

module_name inst_name
     ( .id_out('{id0, id1}),
       .* );

%Error: ..._control.v:422: syntax error, unexpected "'{", expecting TYPE-IDENTIFIER

Here is an example from IEEE 1800-2005 doc:

Array literals are syntactically similar to C initializers, but with the replicate operator ({{}} ) allowed.

int n[1:2][1:3] = '{'{0,1,2},'{3{4}}};

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-05-20T12:35:05Z


'{ is a system verilog feature I thought wouldn't really be needed until structures were supported, but I see how this can be useful. I'll look at adding it.

Meanwhile you can just

assign temp_array[0] = id0;
assign temp_array[1] = id1;

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Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2011-05-23T20:39:38Z


Yes, there is an obvious workaround. However, it requires a lot of meaningless extra code: I added 30 lines just because of 1 instantiation, which itself requires only 11 lines.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-12-14T03:35:49Z


See #� for the parameter need for this.

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Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2012-03-22T23:32:50Z


Another example:

integer scan_offsets[0:3] = '{ 0, MEM_IF_READ_DQS_WIDTH + MEM_DQ_PER_DQS, MEM_IF_READ_DQS_WIDTH, MEM_IF_READ_DQS_WIDTH + MEM_DQ_PER_DQS + 1 };

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Original Redmine Comment
Author Name: Iztok Jeras (@jeras)
Original Date: 2012-05-11T16:21:19Z


Hi,

This feature is now called "Assignment patterns". In addition to arrays and structures it can be used on 1D vectors.

The next example can be used to test the the feature applied to 1D vectors:
test_regress/t/t_assignment_pattern.v
the test can be found at (branch test_sv):
https://github.com/jeras/verilator

Regards, Iztok Jeras

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-08-12T19:14:32Z


The structure version of '{} is in git towards 3.841. Hope to get to array '{} shortly.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-03-31T00:47:01Z


'{} to arrays is in git towards 3.857.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-11T21:09:57Z


In 3.860.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
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