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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2008-10-15T15:44:26Z
No as this is a very rare practice - do you work for IBM? ;) But if you want to fix it yourself, I'll point you to what to change and take the patches.
The big problem is C itself is big-bit-endian in that variable shift operations assume bit 0 is the LSB.
That's fixable by Verilator adding a subtraction at every shift, but the user would still need to know that the bits observed coming out of the model would be numbered in the C, not Verilog way.
Author Name: Rafael Shirakawa
Original Redmine Issue: 36 from https://www.veripool.org
Original Date: 2008-10-15
Hello,
is there any forecast to verilator accept little bit-endian?
regards,
Rafael
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