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Issue #364

blocking & non-blocking assigns -- verilator issues error when no logical conflict exists

Added by John Stevenson about 8 years ago. Updated about 1 month ago.

Status:
Feature
Priority:
Low
Assignee:
Category:
Unsupported
% Done:

0%


Description

In regards to the following error message:
Unsupported: Blocked and non-blocking assignments to same variable
It was issued in error. To reproduce, do the following:
// pseudo-code:
logic [31:0] shiftreg [10];
assign shiftreg[0] = input;
for( i = 1; i < 10; i++ ) begin
   always_ff @(posedge clk) begin
      shiftreg[ i ] <= shiftreg[ i - 1 ];
   end
end
There is no logical conflict:

... shiftreg[ 0 ] has a blocking assign

... shiftreg[ 1 to 9 ] have non-blocking

History

#1 Updated by Wilson Snyder about 8 years ago

  • Category set to Unsupported
  • Status changed from New to Feature
  • Priority changed from Normal to Low

Unfortunately this is a known limitation that's not going to be fixed soon; this case is shown in the manual under BLKANDNBLK. Verilator does all scheduling presently by variable not by individual bits (for speed) so it complains when all bits aren't handled the same way. Sorry. It's on the medium term list of things to improve.

#2 Updated by Alex Solomatnikov about 8 years ago

Temporary workaround is to convert packed array to unpacked array. Of course, this can cause other problems with other tools.

#3 Updated by Alex Solomatnikov over 7 years ago

Is this issue resolved as part of DETECTARRAY issue fix?

Seems to compile and run correctly now.

#4 Updated by Wilson Snyder over 7 years ago

  • Status changed from Feature to Resolved
  • Assignee set to Wilson Snyder

Yes, fixed in git towards 3.833.

#5 Updated by Alex Solomatnikov over 7 years ago

Apparently, I was wrong - it sill does not work in some cases, e.g.:

   always_ff @(posedge clk) begin
      integer k;

      for( k=0; k<RATIO-1; k++ ) begin
         if( en[k] ) begin
            full_line[k*`WIDTH +: `WIDTH] <= `CLK2Q rdata;
         end
      end
   end // always_ff @
   assign full_line[(RATIO-1)*`WIDTH +: `WIDTH] = rdata;

I got:

%Error-BLKANDNBLK: ...: Unsupported: Blocked and non-blocking assignments to same variable: full_line
%Error-BLKANDNBLK: ..: Unsupported: Blocked and non-blocking assignments to same variable: full_line

#6 Updated by Alex Solomatnikov over 7 years ago

I should add that in previous example variables are defined as simple vectors:

   logic [`WIDTH-1:0]       rdata;
   logic [RATIO*`WIDTH-1:0] full_line;

#7 Updated by Wilson Snyder over 7 years ago

  • Status changed from Resolved to Assigned

The fixed note should have mentioned it fixes only arrays used in this context. I'll leave the bug open until the more general fix is made.

#8 Updated by Roman Popov about 1 month ago

I wonder if some simple fix can be invented here, like splitting array into 2 arrays internally, one modeling a register, and one modeling a wire.

So far all of large designs I've tried fail in Verilator with this error. Looks like its quite a common coding practice.

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