blocking & non-blocking assigns -- verilator issues error when no logical conflict exists
Unsupported: Blocked and non-blocking assignments to same variableIt was issued in error. To reproduce, do the following:
// pseudo-code: logic [31:0] shiftreg ; assign shiftreg = input; for( i = 1; i < 10; i++ ) begin always_ff @(posedge clk) begin shiftreg[ i ] <= shiftreg[ i - 1 ]; end endThere is no logical conflict:
... shiftreg[ 0 ] has a blocking assign
... shiftreg[ 1 to 9 ] have non-blocking
#1 Updated by Wilson Snyder about 8 years ago
- Category set to Unsupported
- Status changed from New to Feature
- Priority changed from Normal to Low
Unfortunately this is a known limitation that's not going to be fixed soon; this case is shown in the manual under BLKANDNBLK. Verilator does all scheduling presently by variable not by individual bits (for speed) so it complains when all bits aren't handled the same way. Sorry. It's on the medium term list of things to improve.
#5 Updated by Alex Solomatnikov over 7 years ago
Apparently, I was wrong - it sill does not work in some cases, e.g.:
always_ff @(posedge clk) begin integer k; for( k=0; k<RATIO-1; k++ ) begin if( en[k] ) begin full_line[k*`WIDTH +: `WIDTH] <= `CLK2Q rdata; end end end // always_ff @ assign full_line[(RATIO-1)*`WIDTH +: `WIDTH] = rdata;
%Error-BLKANDNBLK: ...: Unsupported: Blocked and non-blocking assignments to same variable: full_line %Error-BLKANDNBLK: ..: Unsupported: Blocked and non-blocking assignments to same variable: full_line
#8 Updated by Roman Popov about 1 month ago
I wonder if some simple fix can be invented here, like splitting array into 2 arrays internally, one modeling a register, and one modeling a wire.
So far all of large designs I've tried fail in Verilator with this error. Looks like its quite a common coding practice.
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