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Issue #365

bidrectional arrays not supported as module ports

Added by John Stevenson almost 8 years ago. Updated over 1 year ago.

Status:
Feature
Priority:
Normal
Assignee:
-
Category:
Unsupported
% Done:

0%


Description

the following will not compile, i.e., such constructs work with logic/wire, but not with inout
// pseudo-code
module t ( inout [63:0] foo [5] );
   generate
      for (genvar i = 0; i < 5; i++ ) begin
         instantiated_thing u_thing( foo[i] );
      end
   endgenerate
endmodule

module instantiated_thing (inout[63:0] v);
   initial begin
      $display("v=%x", v);
      v = 64'h123456789;
   end
endmodule

History

#1 Updated by Wilson Snyder almost 8 years ago

  • Category set to Unsupported
  • Status changed from New to Assigned

Lane hopes to have some time over the next months to look at this.

#2 Updated by Wilson Snyder over 1 year ago

  • Description updated (diff)

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