Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Support bidirectional arrays as module ports #365

Closed
veripoolbot opened this issue Jul 8, 2011 · 2 comments
Closed

Support bidirectional arrays as module ports #365

veripoolbot opened this issue Jul 8, 2011 · 2 comments
Labels
effort: weeks Expect this issue to require weeks or more of invested effort to resolve resolution: abandoned Closed; not enough information or otherwise never finished type: feature-IEEE Request to add new feature, described in IEEE 1800

Comments

@veripoolbot
Copy link
Contributor

Author Name: John Stevenson
Original Redmine Issue: 365 from https://www.veripool.org

the following will not compile, i.e., such constructs work with logic/wire, but not with inout

// pseudo-code
module t ( inout [63:0] foo [5] );
    generate
       for (genvar i = 0; i < 5; i++ ) begin
          instantiated_thing u_thing( foo[i] );
       end
    endgenerate
endmodule

module instantiated_thing (inout[63:0] v);
    initial begin
       $display("v=%x", v);
       v = 64'h123456789;
    end
endmodule
@veripoolbot
Copy link
Contributor Author

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-07-21T11:33:26Z

Lane hopes to have some time over the next months to look at this.

@veripoolbot veripoolbot added effort: weeks Expect this issue to require weeks or more of invested effort to resolve type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
@wsnyder wsnyder changed the title bidrectional arrays not supported as module ports Support bidrectional arrays as module ports Apr 5, 2020
@wsnyder wsnyder changed the title Support bidrectional arrays as module ports Support bidirectional arrays as module ports Apr 5, 2020
@wsnyder wsnyder added the resolution: abandoned Closed; not enough information or otherwise never finished label May 27, 2023
@wsnyder
Copy link
Member

wsnyder commented May 27, 2023

Closing due to age; unlikely to get supported anytime soon, if someone wants to contribute a patch please reopen.

@wsnyder wsnyder closed this as completed May 27, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
effort: weeks Expect this issue to require weeks or more of invested effort to resolve resolution: abandoned Closed; not enough information or otherwise never finished type: feature-IEEE Request to add new feature, described in IEEE 1800
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
2 participants
@wsnyder @veripoolbot