Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

sensitivity list #37

Closed
veripoolbot opened this issue Oct 17, 2008 · 3 comments
Closed

sensitivity list #37

veripoolbot opened this issue Oct 17, 2008 · 3 comments
Labels
resolution: fixed Closed; fixed

Comments

@veripoolbot
Copy link
Contributor

Author Name: Rafael Shirakawa
Original Redmine Issue: 37 from https://www.veripool.org
Original Date: 2008-10-17

Hi,

Can verilator support sensitivity list with edges and activity wires?

like this example will generate an error:

module example;

wire a;
wire b;
wire c;


always @(a or negedge b) 
begin
  if ( b == 1'b0)
  begin
     c = a;
  end
end

endmodule

and this other one will translate without any error:

module example;

wire a;
wire b;
wire c;


always @(a) 
begin
  if ( b == 1'b0)
  begin
     c = a;
  end
end

always @(negedge b) 
begin
  if ( b == 1'b0)
  begin
     c = a;
  end
end

endmodule
@veripoolbot
Copy link
Contributor Author

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2008-10-17T15:31:47Z

No, that doesn't map to an obvious hardware construct. Perhaps I'm missing something?

If you're making a latch, you should just use

    "always @ (a or b)" or "always @*"

@veripoolbot
Copy link
Contributor Author

Original Redmine Comment
Author Name: Rafael Shirakawa
Original Date: 2008-10-21T15:31:11Z

Yes, you're right, I've checked what this code is doing in my model and it happens to be part of a behavioral memory model, so it is not synthesized... sorry for opening this issue. <@:)

by the way, is there any forecast for Verilator to support some behavioral code, like real variables?

@veripoolbot
Copy link
Contributor Author

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2008-10-29T01:05:14Z

Closed as not behavioral.

As for real variables, they too aren't synthesizable. If someone were to contribute code to support this, I would take it though. It's a fair amount of work, since reals affect so many operators. I can provide direction if you want to undertake this effort.

@veripoolbot veripoolbot added the resolution: fixed Closed; fixed label Dec 22, 2019
@veripoolbot veripoolbot mentioned this issue Dec 22, 2019
Closed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
resolution: fixed Closed; fixed
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@veripoolbot