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AUTO problems with ports of type array of structures #373

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veripoolbot opened this issue Aug 9, 2011 · 3 comments
Closed

AUTO problems with ports of type array of structures #373

veripoolbot opened this issue Aug 9, 2011 · 3 comments
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Author Name: David Rogoff
Original Redmine Issue: 373 from https://www.veripool.org
Original Date: 2011-08-09
Original Assignee: Wilson Snyder (@wsnyder)

Hi guys.
I'm using ports of type structure in my design. If it's just a structure, it's fine. However, if I have an array of structure, the AUTOINST and AUTOREGINPUT get confused and add an extra port/signal with the name of the typedef and not the structure instance.

Also, AUTOINST groups struct ports with interfaces. I don't know if this is intentional and if you want to separate these.

Thanks much,

David

Here are my files:
structs.vh:
typedef struct packed {
logic [7:0] data;
logic wr_ena;
} mystruct_s;

submod.v:

`include "structs.vh"

module submod
(input logic a_port,
input logic [4:0] b_bus,
input mystruct_s single_struct_is_fine,
input mystruct_s [2:0] array_of_struct_is_not,
output logic status);

/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire                 status                  = 1'h0;
// End of automatics

endmodule // submod

top.v:
`include "structs.vh"

module top;

/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic                status;                 // From submod0 of submod.v
// End of automatics

/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
logic                a_port;                 // To submod0 of submod.v
logic                array_of_struct_is_not; // To submod0 of submod.v
logic [4:0]          b_bus;                  // To submod0 of submod.v
logic                mystruct_s [2:0];       // To submod0 of submod.v
// End of automatics

submod submod0
    (/*AUTOINST*/
     // Interfaces
     .single_struct_is_fine          (single_struct_is_fine),
     // Outputs
     .status                         (status),
     // Inputs
     .a_port                         (a_port),
     .b_bus                          (b_bus[4:0]),
     .mystruct_s                     (mystruct_s),
     .array_of_struct_is_not         (array_of_struct_is_not));

endmodule // top
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-08-09T20:03:03Z

I believe you're missing

// Local Variables:
// verilog-typedef-regexp: "_s$"
// End:

With that it should be much better, let me know.

@veripoolbot
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Original Redmine Comment
Author Name: David Rogoff
Original Date: 2011-08-09T20:17:24Z

Wow - that was fast!

Yes, that works great. I didn't know about this variable. Any chance of supporting struct ports in AUTOREG?

Thanks again - David

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-08-09T23:32:20Z

I'm not sure what you mean about struct ports in AUTOREG; would you mind filing another bug with an example.

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