module example;

wire clk;
wire a [9:0];
reg [1:0] b [9:0];
integer j;

generate
     genvar i;
     for (i=0; i<2; i=i+1) begin
         always @(posedge clk) begin
             for (j=0; j<10; j=j+1) begin
                 if (a[j])
                     b[i][j] <= 1'b0;
                 else
                     b[i][j] <= 1'b1;
             end
         end
     end
endgenerate

endmodule