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I've got a ton of signals and ports that are various typedefs/structs. When verilog-mode indents these, it doesn't recognize the types and doesn't indent them properly. For example:
Author Name: David Rogoff
Original Redmine Message: 562 from https://www.veripool.org
Hi again.
I've got a ton of signals and ports that are various typedefs/structs. When verilog-mode indents these, it doesn't recognize the types and doesn't indent them properly. For example:
Is there some way to let verilog-mode know about my data types? Something like what verilog-typedef-regexp does for AUTOs?
Thanks!
David
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