New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
%Error: Internal Error: ...: ../V3AstNodes.h:453: Unexpected Call #393
Comments
Original Redmine Comment In propagating constants between gates, there's some array (oct_rzqin?) that is constant in some way it has never encountered before. Assuming nothing obvious comes to your mind, please attach the highest number .tree file, thanks. |
Original Redmine Comment Yes, oct_rzqin is an array pin, that is unconnected few levels below in the hierarchy. I did save a couple of .tree files before and after failing step, however, both are ~10 MB and |
Original Redmine Comment Please, let me know how to send you those .tree files. |
Original Redmine Comment Attached gziped files. |
Original Redmine Comment This assignment
is causing the error; the ARRAYSEL should be a SEL. I suspect the error is with inlining related to the generate; can you send the *_link.tree |
Original Redmine Comment BTW a work around would probably be to simply tie the pin to zero
|
Original Redmine Comment Yes, we used this workaround. It turns out there was a bug in Verilog and that was the reason verilator was failing. Chandan reduced the test case to the following code:
P.S. I can still send you by email gziped tar ball of .tree files of the original code but it is large ~15 MB |
Original Redmine Comment To clarify, the RTL bug is that the signal "foo" in module "top" in the test case should be arrayed but is not. |
Original Redmine Comment Error for the bad array code added in git towards 3.845. |
Author Name: Alex Solomatnikov
Original Redmine Issue: 393 from https://www.veripool.org
Original Date: 2011-09-20
Original Assignee: Wilson Snyder (@wsnyder)
Last phase before failure:
Attaching full log file and the last few files generated in obj_dir.
Verilator version 3.820+ (after bug 374 was fixed).
Verilog line where verilator fails:
The text was updated successfully, but these errors were encountered: