use strict;
use warnings;
use Verilog::Netlist;

1. prepare netlist
my $nl = new Verilog::Netlist(keep_comments => 1,);
$nl->read_file(filename => './top.v');

1. read in any sub modules
$nl->link();
$nl->lint();
$nl->exit_if_error();

print "Module names in netlist:\n";
for my $mod ( $nl->modules() ) {
    print $mod->name(), "\n";
}
print "\n";

for my $mod ( $nl->top_modules_sorted() ) {
    show_hier($mod, '', '', '');
}

sub show_hier {
    # Recursively descend through module hierarchy,
    # printing each module name and full hierarchical
    # specifier, all module port names, and all
    # instance port connections.
    my $mod      = shift;
    my $indent   = shift;
    my $hier     = shift;
    my $cellname = shift;
    if ($cellname) {
        $hier .= ".$cellname";
    }
    else {
        $hier = $mod->name();
    }
    print "${indent}ModuleName=", $mod->name(), "  HierInstName=$hier\n";
    $indent .= '   ';

    for my $sig ($mod->ports_sorted()) {

        print $indent, 'PortDir=', sigdir($sig->direction()), ' PortName=', $sig->name(), "\n";
        print $indent,  ' Port comment=', $sig->comment(), "\n";
    }

    for my $cell ($mod->cells_sorted()) {
        for my $pin ($cell->pins_sorted()) {
            print $indent, ' PinName=', $pin->name(), ' NetName=', $pin->netname(), "\n";
        }

        show_hier($cell->submod(), $indent, $hier, $cell->name()) if $cell->submod();
    }
}

sub sigdir {
    # Change "in"  to "input"
    # Change "out" to "output"
    my $dir = shift;
    return ($dir eq 'inout') ? $dir : $dir . 'put';
}

Module names in netlist:
buff
inv
top

ModuleName=top  HierInstName=top
    ModuleName=buff  HierInstName=top.b0
       PortDir=input PortName=buf_in
Use of uninitialized value in print at test.pl line 47, <DATA> line 98.
        Port comment=
       PortDir=inout PortName=out
Use of uninitialized value in print at test.pl line 47, <DATA> line 98.
        Port comment=
        PinName=in NetName=buf_in
        PinName=out NetName=a
       ModuleName=inv  HierInstName=top.b0.i0
          PortDir=input PortName=in
Use of uninitialized value in print at test.pl line 47, <DATA> line 98.
           Port comment=
          PortDir=output PortName=out
Use of uninitialized value in print at test.pl line 47, <DATA> line 98.
           Port comment=
        PinName=in NetName=a
        PinName=out NetName=buf_out
       ModuleName=inv  HierInstName=top.b0.i1
          PortDir=input PortName=in
Use of uninitialized value in print at test.pl line 47, <DATA> line 98.
           Port comment=
          PortDir=output PortName=out
Use of uninitialized value in print at test.pl line 47, <DATA> line 98.
           Port comment=