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Author Name: Zeev Brunin
Original Redmine Issue: 425 from https://www.veripool.org
Original Date: 2011-12-18
Original Assignee: Wilson Snyder (@wsnyder)
Is verilog-perl is going to support verilog2K generate ?
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-12-18T23:15:17Z
In what respect?
It parses all of SystemVerilog 2009.
If you're looking for vhier to expand them, then it is unlikely to be the intent to ever do this; see the Verilog-Perl manpage on "Which Parser Package".
Original Redmine Comment
Author Name: Zeev Brunin
Original Date: 2011-12-19T06:09:34Z
When I build a netlist and trying to get a hierarchical path to a generated module
the concatenation of cell names gives me a single path to the module.
What I need is a different path for every generated unit.
Author Name: Zeev Brunin
Original Redmine Issue: 425 from https://www.veripool.org
Original Date: 2011-12-18
Original Assignee: Wilson Snyder (@wsnyder)
Is verilog-perl is going to support verilog2K generate ?
The text was updated successfully, but these errors were encountered: