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Author Name: Chris Randall
Original Redmine Issue: 426 from https://www.veripool.org
Original Date: 2011-12-23
Hi:
I'm trying to write a tool that will pre-process a verilog file, but leave a particular set of ifdefs in the file, eg:.
module blah()
ifdef LEAVE_ME ... endif
ifdef PRE_PROCESS_ME .. endif
endmodule
I'd want the output to include the `ifdef LEAVE_ME line, but either include (or not) the PRE_PROCESS_ME -- I couldn't find a hook that would allow me to do in your modules -- could you point me in the correct direction, please?
I also want all includes and all defines expand -- but I suspect for maximum genericty we should consider the ability of not doing it for all of them.
Cheers.
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-12-23T14:48:41Z
I moved this to under Verilog-Perl, as I presume your intent is to extend vppreproc. The same thing could be done with "verilator -E" but vppreproc seems the more extendable solution.
If I understand properly there would be a new "vppreproc --keep-ifdef FOO" where all references to "ifdef/ifndef/`elsif FOO" etc would remain in the output.
To implement this, working from the top down
make a test case in the t/ directory - this will obviously fail until implemented :) Be sure the test includes the elsif cases noted below.
add the option including documentation to vppreproc; the option would set opt_pp_flags->{keep_ifdef}{$NAME} = 1 for each passed option.
In Preproc.pm document the keep_ifdef, add a new function def_keep that tests that hash and returns true.
Plumb def_keep into the .h, .cpp, .xs similar to how def_value is done though
def_keep can return a bool. (See also defExists)
In V3Preproc under 'case ps_DEFNAME_IFDEF:' you'd call defKeep() and if set
buf= a string with "`ifdef "+ the define name to yyourtext, then return VP_TEXT; (i.e. return the text to print rather than do the ifdef)
ENDIF/ELSIF needs to know defKeep() was set for that level; remember defKeep in the VPreIfEntry structure. ELSIF is a bit complicated as you may need to convert it to a ifndef/ifdef (All the permutations of if REMOVING elsif REMOVING, if NOT_REMOVING elsif REMOVING, etc.)
Seems like a lot but shouldn't take too long as it's almost all plumbing.
Start with the git version, as I did a small refactoring to make this easier.
Author Name: Chris Randall
Original Redmine Issue: 426 from https://www.veripool.org
Original Date: 2011-12-23
Hi:
I'm trying to write a tool that will pre-process a verilog file, but leave a particular set of ifdefs in the file, eg:.
module blah()
ifdef LEAVE_ME ...
endififdef PRE_PROCESS_ME ..
endifendmodule
I'd want the output to include the `ifdef LEAVE_ME line, but either include (or not) the PRE_PROCESS_ME -- I couldn't find a hook that would allow me to do in your modules -- could you point me in the correct direction, please?
I also want all includes and all defines expand -- but I suspect for maximum genericty we should consider the ability of not doing it for all of them.
Cheers.
The text was updated successfully, but these errors were encountered: