Author Name: Lane Brooks
Original Redmine Issue: 43 from https://www.veripool.org
Original Date: 2008-11-12
Original Assignee: Wilson Snyder (@wsnyder)

I discovered in verilator that it is possible to select into a wire out side of its boundaries and the selection wraps. e.g.:

wire [1:0] in;
wire [1:0] out32 = in[3:2];
wire [1:0] out10 = in[1:0];

out10 and out32 come out equal. I am not sure what the verilog standard says, but I think I am used to this giving an error in other tools. I have attached a test that shows the behavior.