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Incorrect indentation in Verilog Mode v736 #430

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veripoolbot opened this issue Jan 5, 2012 · 5 comments
Closed

Incorrect indentation in Verilog Mode v736 #430

veripoolbot opened this issue Jan 5, 2012 · 5 comments
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Author Name: Alan Morgan
Original Redmine Issue: 430 from https://www.veripool.org
Original Date: 2012-01-05

I have noticed this incorrect indentation of code lines that are generated by AUTORESET, if they are subsequently re-indented after AUTORESET creates them. Here is an example code fragment:

module ar_misalign;

    parameter SBW = 19;
    
    reg [2:0]            f_state;
    reg [(SBW-1):0]      tag_read;
    reg                  flush_ip;
    reg                  fetch_go;
    reg                  fetch_tag_rd_req;
    reg                  ti_mb_ready;

    always @(posedge clk or negedge rst_n)
       if (!rst_n) begin
          /*AUTORESET*/
          // Beginning of autoreset for uninitialized flops
          f_state <= 3'h0;
          fetch_go <= 1'h0;
          fetch_tag_rd_req <= 1'h0;
          flush_ip <= 1'h0;
          tag_read <= {(1+((SBW-1))){1'b0}};
ti_mb_ready <= 1'h0;
// End of automatics
end
       else begin
          // dummy code for example
          f_state <= 3'h3;
          fetch_go <= 1'h1;
          fetch_tag_rd_req <= 1'h1;
          flush_ip <= 1'h1;
          tag_read <= 14;
          ti_mb_ready <= 1'h1;
       end


endmodule // ar_misalign

You see that the last three lines of the reset assignments are not indented at all. AUTORESET generated them correctly, but they become incorrect if re-indented, either individually by hitting TAB on those lines, or by using C-M-\ to re-indent a region.
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Original Redmine Comment
Author Name: Alan Morgan
Original Date: 2012-01-10T12:45:09Z

Here's another fragment that shows a similar issue, probably the same bug:

module exp_misalign (/*AUTOARG*/
    // Inputs
    clk
    );

    input clk;

    parameter AWIDTH = 32;
    localparam [0:0] TWO_BYTE_PIXELS = 1'b1;

    
    reg [AWIDTH-1:7] f_mb_chroma_base;
    reg [2:0]        f_partn;
    reg [AWIDTH-1:0] f_raddr;
    reg              a;
    
    always @(posedge clk)
       begin
          f_raddr <= {f_mb_chroma_base[AWIDTH-1:7], 7'h0} |
                     ({{(AWIDTH-7){1'b0}}, f_partn[0], 6'h0} <<
                      TWO_BYTE_PIXELS);
// These lines are not indented
a <= f_partn[1];

end
    
endmodule // exp_misalign

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Original Redmine Comment
Author Name: Warren Ferguson
Original Date: 2012-02-21T22:44:59Z

Same here:

module xxx #(parameter ACTIVE=0) (
`include "xxx.ports.v"
);
t_alu_misc_out BROADCAST_1_REG_4XB;

assign BROADCAST_1_REG_4XB.Result       = {8{src1.Byte[0]}};

assign BROADCAST_1_REG_4XB.DpSp1Flag = '0;
assign BROADCAST_1_REG_4XB.Sp2Flag = '0;
assign BROADCAST_1_REG_4XB.DpSp1MaskOut = '0;
assign BROADCAST_1_REG_4XB.Sp2MaskOut = '0;

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Original Redmine Comment
Author Name: Warren Ferguson
Original Date: 2012-02-23T17:27:41Z

Repeat of previous message, this time with tags.

module xxx (); 
    t_alu_misc_out BROADCAST_1_REG_4XB; 
    assign BROADCAST_1_REG_4XB.DpSp1Flag = '0; 
    assign BROADCAST_1_REG_4XB.Sp2Flag = '0; 
    assign BROADCAST_1_REG_4XB.Result       = {8{src1.Byte[0]}};
assign BROADCAST_1_REG_4XB.DpSp1MaskOut = '0; 
assign BROADCAST_1_REG_4XB.Sp2MaskOut = '0;

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Original Redmine Comment
Author Name: Jalib Ahmed
Original Date: 2013-08-12T10:44:11Z

Im having the same same problem, seems to be caused by the 'replication' operator on the preceding line. I've just downloaded version 840 and the problem has disappeared.

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Original Redmine Comment
Author Name: Alex Reed
Original Date: 2015-03-13T20:52:53Z

Seems to be fixed based on comments in this issue and www.veripool.org/issues/556-Verilog-mode-replication-breaks-alignment

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