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indenting for some forms of SystemVerilog constraints is wrong/odd #433
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Original Redmine Comment wow. the html (or php?) code "displayer" really mangled that code. That's not at all what I pasted. I'll try and with a pre block...
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Original Redmine Comment I made a small set of changes which solve "my problem" (as in, "works for me!" :-) with systemverilog constraints. I'm not 100% happy with the changes, but they are at least minimal and clean.
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Original Redmine Comment As you said, this seems better, but is not perfect. Even so I was ready to commit it, however it breaks basic Verilog indentation with the following, so unfortunately I can't merge it. Attached is a modified version of your patch that just changes a few naming and related issues if you'd like to fix that one instead.
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Original Redmine Comment I noticed that also (but only yesterday). I'll fix that and resubmit. thanks! |
Original Redmine Comment Can you please assign someone to fix this? Any OVM/UVM verification code is extremely annoying to deal with because of this. |
Original Redmine Comment The way things get fixed with open source is you "assign" yourself to fix it. Bruce bluewlvrn@gmail.com submitted another patch (attached), but this still breaks basic indents so cannot be merged. Perhaps you could ask if he needs assistance getting this ready. |
Original Redmine Comment Hello, the constraints indenting is working great now in most cases, however I am seeing an issue with the following snippet:
Could anyone give me any guidance on where to look to go about fixing this? |
Original Redmine Comment Wilson, |
Original Redmine Comment Thanks again, pushed to git. |
Author Name: Brad Parker (@lisper)
Original Redmine Issue: 433 from https://www.veripool.org
Original Date: 2012-01-27
Original Assignee: Alex Reed
indentation for several different forms of SV constraints is wrong or odd;
specifically, empty constraints are odd, as are constraints with "if" followed by braces
It acts like it doesn't understand the braces (i.e. {})
Here's an example:
class data;
rand integer data1;
rand integer data2,data3;
rand reg [31:0] foo;
endclass // data
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