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Indenting comments on declarations in v736 #435

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veripoolbot opened this issue Feb 2, 2012 · 2 comments · Fixed by #1775
Closed

Indenting comments on declarations in v736 #435

veripoolbot opened this issue Feb 2, 2012 · 2 comments · Fixed by #1775
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@veripoolbot
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Author Name: Bruce LaVigne
Original Redmine Issue: 435 from https://www.veripool.org


I don't know when this stopped working, but in v736, comments on declaration lines no longer use comment-column:

Old formatting (good):

module foo (
      // Global Interface Signals
 input					 clk,			// core system clock
 input 					 dclk,			// delayed clock
 input 					 reset_L,		// module reset: global register
.....


New formatting (broken, IMHO):
module foo (
				// Global Interface Signals
	    input clk, // core system clock
	    input dclk, // 0 in kndr
	    input reset_L,		// module reset: global register
	    )

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-02-02T20:46:41Z


There's really two things here.

The first is the space between "input" and the signal name. This was changed in rev562, and is disabled with (setq verilog-auto-lineup nil).

The second is the space between ( and the input keyword. I might be off, but I think it's been this way since before r462 in 2008 when my data starts. I think most people seem to put the ( on a line by itself to work around this.

If you have a specific version that shows the second indent not occurring, please let me know the rev number.

@veripoolbot
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Original Redmine Comment
Author Name: Bruce LaVigne
Original Date: 2012-02-02T21:07:04Z


Wilson,
Thanks for the quick reply, but in creating the test case I think I confused the issue. I am not concerned with the space between the beginning of line and the input keyword, nor with the space between the keyword and the signal name. What I am trying to get right (and used to work) was the space between the end of the signal (actually, the comma) and the beginning of the comment. Verilog-mode used to honor the emacs "comment-column", and in fact, it seems to try to do this if you hit "tab" on an individual line; however, in aligning the comment on the current line (via electric-verilog-tab), it messes up any other comments on lines above/below it!

Here is another example. In this case, I started with all the comments in column 32 (the emacs default comment-column). When I hit "tab" on any one line, the entire block of declarations has their comments adjusted to one space after the comma. Then, if I hit "tab" a second time, the current line I am on will get a properly indented comment at column 32. But, as soon as I try to do this on another line, that one moves back! I tried performing the "verilog-indent-buffer" all at once, but no luck there, either.

Thanks for looking into this!

module foo
(
				// Global Interface Signals
 input clk, // core system clock
 input signal1, // Comment here which should be at "comment-column"
 input signal_long2, // Comment here which should be at "comment-column"
 input sig3,			// Here, I've hit "tab" twice and this line is correct
 input s4, // Comment here which should be at "comment-column"
 input reset_L,		// module reset: global register

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