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Author Name: VNS BLORE
Original Redmine Issue: 438 from https://www.veripool.org
Original Date: 2012-02-08
Original Assignee: Wilson Snyder (@wsnyder)
Source code (before auto-expansion)
module top (/*AUTOARG*/);
supply1 vdd_wire;
supply0 vss_wire;
inst_module inst (
.VDD(vdd_wire),
.VSS(vss_wire),
endmodule
module inst_module (input VDD,
input VSS
);
endmodule
The issues is -
1) supply1,supply0 are implicit verilog datatypes similar to wires.
2) AUTOREG should treat supply, supply0 similar to wires and include them in the expanded port list.
Code after auto-expansion:
module top (
input supply1,
input supply0
);
supply1 vdd_wire;
supply0 vss_wire;
inst_module inst (
.VDD(vdd_wire),
.VSS(vss_wire),
endmodule
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-02-13T13:26:37Z
Your example doesn't make sense as AUTOARG doesn't insert "input". But anyhow I think I know what you're after; supply0/1 were special cased for a historic reason that should no longer apply.
Author Name: VNS BLORE
Original Redmine Issue: 438 from https://www.veripool.org
Original Date: 2012-02-08
Original Assignee: Wilson Snyder (@wsnyder)
Source code (before auto-expansion)
The text was updated successfully, but these errors were encountered: