Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-02-27T16:07:25Z

Perhaps you're looking for verilog-auto-inst-param-value?

Original Redmine Comment
Author Name: Omri Sharon
Original Date: 2012-02-28T09:30:20Z

Hi,
the verilog-auto-inst-param-value seems to be for parameters, not defines.

i've tried it, but there was no change. but there might be something else blocking it (i'm only starting to learn the verilog-mode.el file...)

thx

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-02-28T12:04:08Z

Sorry, you're right. It's possible this could be extended, however it would have the same restriction as with parameters, notably that code like this

 `ifdef something
  `define foo bar
 `else
  `define foo baz
 `endif
 ..... `foo

will always use baz for foo, which is probably not what you want.

Original Redmine Comment
Author Name: Omri Sharon
Original Date: 2012-02-28T13:31:55Z

Actually i just wanted my top to not have defines in the ports, so that whoever instantiate me doesn't need to know or read my define files.

Thx for the help.

Original Redmine Comment
Author Name: K W
Original Date: 2018-11-09T16:00:07Z

i'm coming late into this. Does autos read the `include "foo_file.v" and takes the defines for example:

`define FOO bar

and replace every define `FOO with bar in the top level file?

I want to replace the `FOO from the port names with the actual values.

Thanks!

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-11-10T13:38:33Z

If you have `defines in a include file then do this in the parent file

// Local Variables:
// verilog-auto-read-includes:t
// End:

and any usages of defines in ranges will be expanded.

Original Redmine Comment
Author Name: K W
Original Date: 2018-11-12T14:25:57Z

I tried this on a test code but i didn't get the expected results.

In test_defines.v:

`define FOO 32

In data_sel.v which calls test_defines.v:

`include "test_defines.v"

module data_sel
  (/*AUTOARG*/
    // Outputs
    dataout,
    // Inputs
    selA, datain_0, datain_1
    );

    input selA;
    input datain_0[`FOO-1:0];
    input datain_1[`FOO-1:0];
    output dataout[`FOO-1:0];
    
    always @(/*AS*/datain_0 or datain_1 or selA)
      begin
	if (selA) 
	  dataout = datain_0;
	else
	  dataout = datain_1;
      end
    

endmodule // data_sel
// Local Variables:
// verilog-auto-read-includes:t
// End:

I had expected the constant 40 would replace `FOO defines in data_sel.v when I performed a C-c C-a.

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-11-14T11:28:48Z

Needed to do some experiments to recall how this works. The replacements occur only in instantiating modules at the instantiation, and only if requested, e.g. make this instantiating file.

`include "test_defines.v"

module x;

    /* data_sel AUTO_TEMPLATE (
     .\(.*\)     (@"(verilog-symbol-detick-text (concat vl-name vl-bits))"),
     ); */

    autoinst_defs_sub sub
      (/*AUTOINST*/
       // Outputs
       .dataout                          (dataout[32-1:0]),       // Templated
       // Inputs
       .selA                             (selA),                  // Templated
       .datain_0                         (datain_0));             // Templated

endmodule

// Local Variables:
// verilog-auto-read-includes:t
// End:

A switch could probably be made do this a little cleaner if need be.

Original Redmine Comment
Author Name: K W
Original Date: 2018-11-14T16:20:48Z

Thanks a bunch! This worked.