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Author Name: Matthias Wagner
Original Redmine Issue: 445 from https://www.veripool.org
Original Date: 2012-02-29
Original Assignee: Wilson Snyder (@wsnyder)
The documentation for AUTOINST says: Templates go ABOVE the instantiation(s). When an instantiation is expanded `verilog-mode' simply searches up for the closest template.
My expectation is that instantiations without previous AUTO_TEMPLATE will use the default port / wire names and that the search stops at the top of the file.
The following example shows that the template for demob_1 is also used for demob_0.
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire xxx; // From demob_0 of demob.v, ...
wire yyy; // From demob_0 of demob.v, ...
// End of automatics
demob demob_0
(/*AUTOINST*/
// Outputs
.b1 (xxx), // Templated
.b2 (yyy)); // Templated
/* demob AUTO_TEMPLATE (
.b1 (xxx),
.b2 (yyy),
);
*/
demob demob_1
(/*AUTOINST*/
// Outputs
.b1 (xxx), // Templated
.b2 (yyy)); // Templated
I have used version 789 to generate the example.
The text was updated successfully, but these errors were encountered:
Author Name: Matthias Wagner
Original Redmine Issue: 445 from https://www.veripool.org
Original Date: 2012-02-29
Original Assignee: Wilson Snyder (@wsnyder)
The documentation for AUTOINST says:
Templates go ABOVE the instantiation(s). When an instantiation is expanded `verilog-mode' simply searches up for the closest template.
My expectation is that instantiations without previous AUTO_TEMPLATE will use the default port / wire names and that the search stops at the top of the file.
The following example shows that the template for demob_1 is also used for demob_0.
I have used version 789 to generate the example.
The text was updated successfully, but these errors were encountered: