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This works fine and appends "happy" to the signal names.
However, my next example is more complicate with a module with a couple of parameters that specify the dimensions of a 2-dimensional port. Here's the sub-module:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-04-20T01:06:49Z
'@@' expands to happy, so you have in lisp (upcase happy), and what you really want is (upcase "happy"). So you need to quote the '@@'.
Verilog-mode knows about the multidimensional array, so in theory it should be able to instantiate the proper connections. AUTOLOGIC I'm not so sure about. Let me try an experiment tomorrow; as usual if I don't get back within a few days please file a bug.
Original Redmine Comment
Author Name: David Rogoff
Original Date: 2012-04-21T02:00:06Z
Thanks Wilson - that worked ... sort-of. First, I had to escape the quotes. That worked fine - for signals. However, the exact same code didn't work for renaming parameters in the AUTOINSTPARAM :( Just a @ worked fine, but the whole upcase thing gave errors! Then, all the odd parentheses and punctuation in the regexps in the template confused the rest of verilog-mode trying to indent and match expressions. I've had problems in the past with verilog-mode getting confused by parentheses in comments. Finally, that same stuff generated errors from the Cadence compiler. I had to wrap the template in an ifdef so it was invisible to the compiler.
Anyway, a ton more time than I thought it would take, but I got it to do what I wanted!
Author Name: David Rogoff
Original Redmine Message: 818 from https://www.veripool.org
This is driving me crazy - please help!
So, I have a module I use several places in another module. I was using templates to rename the port signals with no problem:
This works fine and appends "happy" to the signal names.
However, my next example is more complicate with a module with a couple of parameters that specify the dimensions of a 2-dimensional port. Here's the sub-module:
The first problem is that verilog-mode isn't dealing with this properly. Autoinst expands this to:
So it doesn't see the other dimension. It also defines in wrong in AUTOLOGIC.
So, since I read that there are issues with MDA support in verilog-mode, I gave it some help:
This, of course, instaniated correctly, and declared the signal correctly in AUTOLOGIC.
However... each instance uses different parameters, so I have to use that AUTO_TEMPLATE match in the parameter names:
Which gives this:
The problem is that the parameter names have to be all upper case and the module names lower case so I got "PARAM_Yhappy" instead of "PARAM_YHAPPY" :(
So, I read the FAQ and the help page and try and use the example here:
http://www.veripool.org/wiki/verilog-mode/Faq#How-do-I-use-AUTO_TEMPLATE-to-lower-case-all-signals
``` /* my_mod AUTO_TEMPLATE "my_\([a-z]+\)_mod" ( .\(.*\) (\1_@[]), .port_a (port_a_@[PARAM_X@"(upcase @)"-1:0][PARAM_Y@"(upcase @)"-1:0]),
); */
eval: Symbol's value as variable is void: happy
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