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clocks and signals not recognized in generate loops #45

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veripoolbot opened this issue Nov 22, 2008 · 2 comments
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clocks and signals not recognized in generate loops #45

veripoolbot opened this issue Nov 22, 2008 · 2 comments
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Rodney Sinclair
Original Redmine Issue: 45 from https://www.veripool.org
Original Date: 2008-11-22
Original Assignee: Wilson Snyder (@wsnyder)

The attached source illustrates two error messages associated with clocks and registers within generate statements:



verilator --cc tb1.v tb.cc # bussed clocks

verilator --cc tb2.v tb.cc # bussed output (work around for bussed clocks)

verilator --cc tb3.v tb.cc # work around for both busses
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2008-11-23T00:02:01Z

The first I'll look at supporting.

The second case isn't an error, but a warning

%Warning-MULTIDRIVEN: tb2.v:4: Signal has multiple driving blocks: count

This is a correct warning. While each bit doesn't have a different block the signal does. Verilator doesn't perform bit level analysis of this and it's not something I can work on right now, so you'll need to just turn off the warning; or simply move the initial loop outside the generate.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2008-11-23T02:15:17Z

The below patch should fix this. It will be in the next release, which is fairly major, so it is likely to be a few weeks.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
This was referenced Dec 22, 2019
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
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