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Support for checking endmodule identintifiers #450

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veripoolbot opened this issue Mar 7, 2012 · 2 comments
Closed

Support for checking endmodule identintifiers #450

veripoolbot opened this issue Mar 7, 2012 · 2 comments
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area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed

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@veripoolbot
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Author Name: Iztok Jeras (@jeras)
Original Redmine Issue: 450 from https://www.veripool.org
Original Date: 2012-03-07
Original Assignee: Wilson Snyder (@wsnyder)


Hi,

Currently identifiers at the end of the module are allowed but not checked. NCsim creates a warning, but this could also be a lint error, since it is very easy to fix.

The next constructs should support end identifiers (not sure which are or will be implemented in verilator):
module/endmodule
package/endpackage
interface/endinterface
covergroup/endgroup
config/endconfig
program/endprogram
class/endclass
function/endfunction
task/endtask
property/endproperty
sequence/endsequence
begin/end (inside generate, always, fork/join, ... blocks)
primitive/endprimitive
fork/join|join_any|join_none
clocking/endclocking

The next tests at least partially test this issue:
test_regress/t/t_hierarchy_identifier.pl
test_regress/t/t_hierarchy_identifier_bad.pl (should report a warning or error)
test are available at:
https://github.com/jeras/verilator

Regards,
Iztok Jeras

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-08T01:20:04Z


Added ENDLABEL warning in git towards 3.832.

Also merged in your test case(s), thanks much.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-08T04:07:21Z


In 3.832.

@veripoolbot veripoolbot added area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed labels Dec 22, 2019
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Labels
area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed
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