Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-09T00:27:15Z

I tried this on other simulators and posted new fixed macros on the forum.

As I noted there they didn't allow assignments to wires, so these should be made read only:

`RW_ACCESS ([0:0], c,     {t.i_test_sub.c});
`RW_ACCESS ([7:0], d,     {t.i_test_sub.d});
`RW_ACCESS ([5:0], d_slice, {t.i_test_sub.d[6:1]});
                         t.i_test_sub.mem[32][2:0]});

Also generally I'd like to avoid "magic logfile" tests. If it's not too hard can you check the
values at runtime? This makes it easier to test against other simulators, and also allows me to
comment out sections of the test when debugging. (Note how many tests have a `ifdef TEST_VERBOSE
around displays.)

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-24T14:31:43Z

Would you like to make the updates mentioned in the last post (the read only and self testing) so I could add this to regressions?

Original Redmine Comment
Author Name: Jeremy Bennett (@jeremybennett)
Original Date: 2012-03-27T17:41:08Z

Apologies - fell off the stack.

New version attached as diff against current git HEAD (commit 996f48f). Now no longer tests for writes to wires (Verilator ought to flag this). A successful test now just prints the "All Finished" message unless run with --verbose when it also produces lots of output.

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-28T00:08:05Z

Great, in git towards 3.833, thanks.