signal not generated in state machine #46
Labels
area: wrong runtime result
Issue involves an incorrect runtine result from Verilated model
resolution: fixed
Closed; fixed
Author Name: Rodney Sinclair
Original Redmine Issue: 46 from https://www.veripool.org
Original Date: 2008-12-27
Original Assignee: Wilson Snyder (@wsnyder)
The attached code demonstrates a problem with state machines using Verilator 3.681.
After the strobe "myevent", the signal "myevent_pending" should go high for at least one clock cycle, after which STATE_ONE should be entered. The code in tb1.v should have this behavior but it does not -- STATE_ONE is entered immediately after the strobe "myevent". The work around in tb2.v does not have this problem.
To demonstrate:
make -f tb1.mk
obj_dir/Vtb
-- examine "myevent_pending"
make -f tb2.mk
obj_dir/Vtb
-- examine "myevent_pending"
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