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Issue #461

genvar declaration inside generate

Added by Alex Solomatnikov over 7 years ago. Updated over 7 years ago.

Status:
Closed
Priority:
High
Assignee:
Category:
Unsupported
% Done:

0%


Description

The following code in Altera's IP:

    generate
    genvar a;
    begin : unpack_odt_config // error!!!
        for (a=0; a<CFG_MEM_IF_CHIP; a=a+1)
        begin : unpack_odt_config_per_chip
...
        end
    end
    endgenerate

causes verilator error:

: syntax error, unexpected begin

VCS works fine.

History

#1 Updated by Alex Solomatnikov over 7 years ago

Obviously, low priority - the code can be easily fixed.

#2 Updated by Wilson Snyder over 7 years ago

  • Category set to Unsupported
  • Assignee set to Wilson Snyder
  • Priority changed from Normal to High

This is a bug in verilog-perl also, I will fix it there with high priority first as it is supposed to accept everything.

#3 Updated by Wilson Snyder over 7 years ago

  • Status changed from New to Assigned

#4 Updated by Wilson Snyder over 7 years ago

Verilog-Perl: Fixed in git towards 3.315.

#5 Updated by Wilson Snyder over 7 years ago

  • Status changed from Assigned to Resolved

Verilator fixed in git towards 3.833.

#6 Updated by Wilson Snyder over 7 years ago

  • Status changed from Resolved to Closed

In 3.833.

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