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Author Name: Alex Solomatnikov
Original Redmine Issue: 461 from https://www.veripool.org
Original Date: 2012-03-22
Original Assignee: Wilson Snyder (@wsnyder)
The following code in Altera's IP:
generate
genvar a;
begin : unpack_odt_config // error!!!
for (a=0; a<CFG_MEM_IF_CHIP; a=a+1)
begin : unpack_odt_config_per_chip
...
end
end
endgenerate
causes verilator error:
: syntax error, unexpected begin
VCS works fine.
The text was updated successfully, but these errors were encountered:
Author Name: Alex Solomatnikov
Original Redmine Issue: 461 from https://www.veripool.org
Original Date: 2012-03-22
Original Assignee: Wilson Snyder (@wsnyder)
The following code in Altera's IP:
causes verilator error:
VCS works fine.
The text was updated successfully, but these errors were encountered: