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Parameters outside modules not recognized #471

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veripoolbot opened this issue Mar 27, 2012 · 4 comments
Closed

Parameters outside modules not recognized #471

veripoolbot opened this issue Mar 27, 2012 · 4 comments
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@veripoolbot
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Author Name: Corey Teffetalor
Original Redmine Issue: 471 from https://www.veripool.org
Original Date: 2012-03-27
Original Assignee: Wilson Snyder (@wsnyder)


It seems that "parameter" statements outside of module scope are not recognized by the Verilog-Perl Verilog::Netlist class. This seems to be is rare-but-valid syntax.

Would it be possible to add an interface to Verilog::Netlist to retrieve these global scoped parameters, or assign the "global" parameter net to all Verilog::Module in the Verilog::Netlist structure they apply to. I do not see them stored anywhere in the Verilog::Netlist structures using Data::Dumper.

This seems to have previously been noted at (2nd comment down):
http://www.veripool.org/boards/18/topics/show/410?r=575#message-575

module A( B, C );
input A;
output B;
parameter D = 1; // Can see this.
assign C = A;
endmodule

parameter D = 1; // Can't see this.
module A( B, C );
input A;
output B;
assign C = A;
endmodule

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-27T23:40:55Z


It parses them, just doesn't have a place to put them, as you indicated. I'll make a $root, which is where SystemVerilog says they go.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-28T23:52:06Z


This is fixed in git towards 3.315.

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Original Redmine Comment
Author Name: Corey Teffetalor
Original Date: 2012-04-09T19:05:35Z


Glanced at the git code. Thanks for the quick fix! Should be a good solution to retrieving these parameters.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-05-04T21:50:57Z


In 3.315.

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