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Author Name: Corey Teffetalor
Original Redmine Issue: 471 from https://www.veripool.org
Original Date: 2012-03-27
Original Assignee: Wilson Snyder (@wsnyder)
It seems that "parameter" statements outside of module scope are not recognized by the Verilog-Perl Verilog::Netlist class. This seems to be is rare-but-valid syntax.
Would it be possible to add an interface to Verilog::Netlist to retrieve these global scoped parameters, or assign the "global" parameter net to all Verilog::Module in the Verilog::Netlist structure they apply to. I do not see them stored anywhere in the Verilog::Netlist structures using Data::Dumper.
Author Name: Corey Teffetalor
Original Redmine Issue: 471 from https://www.veripool.org
Original Date: 2012-03-27
Original Assignee: Wilson Snyder (@wsnyder)
It seems that "parameter" statements outside of module scope are not recognized by the Verilog-Perl Verilog::Netlist class. This seems to be is rare-but-valid syntax.
Would it be possible to add an interface to Verilog::Netlist to retrieve these global scoped parameters, or assign the "global" parameter net to all Verilog::Module in the Verilog::Netlist structure they apply to. I do not see them stored anywhere in the Verilog::Netlist structures using Data::Dumper.
This seems to have previously been noted at (2nd comment down):
http://www.veripool.org/boards/18/topics/show/410?r=575#message-575
module A( B, C );
input A;
output B;
parameter D = 1; // Can see this.
assign C = A;
endmodule
parameter D = 1; // Can't see this.
module A( B, C );
input A;
output B;
assign C = A;
endmodule
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