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Issue #471

Parameters outside modules not recognized

Added by Corey Teffetalor almost 8 years ago. Updated almost 8 years ago.

Status:
Closed
Priority:
Normal
Assignee:
% Done:

0%


Description

It seems that "parameter" statements outside of module scope are not recognized by the Verilog-Perl Verilog::Netlist class. This seems to be is rare-but-valid syntax.

Would it be possible to add an interface to Verilog::Netlist to retrieve these global scoped parameters, or assign the "global" parameter net to all Verilog::Module in the Verilog::Netlist structure they apply to. I do not see them stored anywhere in the Verilog::Netlist structures using Data::Dumper.

This seems to have previously been noted at (2nd comment down): http://www.veripool.org/boards/18/topics/show/410?r=575#message-575

module A( B, C ); input A; output B; parameter D = 1; // Can see this. assign C = A; endmodule

parameter D = 1; // Can't see this. module A( B, C ); input A; output B; assign C = A; endmodule

History

#1 Updated by Wilson Snyder almost 8 years ago

  • Status changed from New to Assigned
  • Assignee set to Wilson Snyder

It parses them, just doesn't have a place to put them, as you indicated. I'll make a $root, which is where SystemVerilog says they go.

#2 Updated by Wilson Snyder almost 8 years ago

  • Status changed from Assigned to Resolved

This is fixed in git towards 3.315.

#3 Updated by Corey Teffetalor almost 8 years ago

Glanced at the git code. Thanks for the quick fix! Should be a good solution to retrieving these parameters.

#4 Updated by Wilson Snyder almost 8 years ago

  • Status changed from Resolved to Closed

In 3.315.

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