module submod(
         rst_n,
         clk,
         rst_n_ext
);

parameter STAGES = 4;
parameter NUM_OUT = 1;

input   rst_n;
input   clk;
output  [NUM_OUT-1:0] rst_n_ext;

reg[STAGES+NUM_OUT-2:0] rst_reg;

generate
genvar i;
         for (i=0; i<STAGES+NUM_OUT-1; i=i+1)
         begin
                 always @(posedge clk or negedge rst_n)
                 begin
                         if (~rst_n)
                                 rst_reg[i] <= 1'b0;
                         else
                         begin
                                 if (i==0)
                                         rst_reg[i] <= 1'b1;
                                 else if (i < STAGES)
                                         rst_reg[i] <= rst_reg[i-1];
                                 else
                                         rst_reg[i] <= rst_reg[STAGES-2];
                                 
                         end
                 end
         end
endgenerate

         assign rst_n_ext = rst_reg[STAGES+NUM_OUT-2:STAGES-1];

endmodule


module test(
             input  rst_n,
             input  clk,
             output out
             );

    reg [4-1:0] rst1;

    submod  u1(
                 .rst_n        (rst_n),
                 .clk          (clk),
                 .rst_n_ext    (rst1)
         );
         defparam u1.STAGES  = 5; 
         defparam u1.NUM_OUT = 4;

    reg [1-1:0] rst2;

    submod  u2(
                 .rst_n        (rst_n),
                 .clk          (clk),
                 .rst_n_ext    (rst2)
         );
         defparam u2.STAGES = 5; 

endmodule

verilator -sp -Wno-fatal --top-module test test.v
%Error: test.v:29: Selection index out of range: 7:7 outside 4:0
%Error: test.v:29: Selection index out of range: 7:7 outside 4:0
%Error: Exiting due to 2 error(s)