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%Error: ...: Internal: Blocking <= assignment in non-clocked block, should have converted in V3Active #478

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veripoolbot opened this issue Apr 5, 2012 · 6 comments
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Alex Solomatnikov
Original Redmine Issue: 478 from https://www.veripool.org
Original Date: 2012-04-05
Original Assignee: Wilson Snyder (@wsnyder)


Source code looks like:

     initial
     begin
...
         a1 <= 1'b0;
         a2 <= 0;
         a3 <= 0;
         a4 <= 0;
         a5 <= 1'b0;
         a6 <= 1'b1;
         a7 <= 1'b1; 
         a8 <= 1'b1;                 
         a9 <= 1'b0;
         a10 <= 1'b0;
         a11 <= 0;

verilator complains about these assignments.

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Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2012-04-05T00:24:31Z


There is also an error message in the same initial block about non-blocking assignment to an array

%Error-BLKLOOPINIT: ...: Unsupported: Delayed assignment to array inside for loops (non-delayed is ok - see docs)

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Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2012-04-05T01:03:12Z


After I tried to convert non-blocking assignments <= to blocking =, I get:

%Error-BLKANDNBLK: ...: Unsupported: Blocked and non-blocking assignments to same variable: ...

Apparently, in this behavioral model some state registers are initialized using initial block. There is no way to compile this model with verilator because non-blocking assignment in initial block causes internal error and blocking assignment in initial block causes this error.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-04-05T01:07:43Z


In the BLKANDNBLK case, even though these are errors you can turn them off like you would a warning; this is because Verilator won't be modeling them as would be a normal simulator that honors the <= delays. Probably both <= and = should be allowed in initial blocks without warnings.

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Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2012-04-05T01:21:13Z


My last message was wrong and should be disregarded: in fact Error-BLKANDNBLK is related to different module.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-04-27T00:40:24Z


Added a new INITIALDLY warning you can suppress if you wish.

Fixed in git towards 3.840++.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-07-31T22:54:23Z


In 3.840.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
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