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Support for SystemVerilog "parameter type" #480

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veripoolbot opened this issue Apr 8, 2012 · 2 comments
Closed

Support for SystemVerilog "parameter type" #480

veripoolbot opened this issue Apr 8, 2012 · 2 comments
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Iztok Jeras (@jeras)
Original Redmine Issue: 480 from https://www.veripool.org
Original Date: 2012-04-08

Hi,

The SystemVerilog feature "Parameter type" is not yet supported, I created a test for it. The provided test creates various instances of a module where one of the ports has a parameterized type. This parameter is different for each module instance. Modules report back the width of the parameterized port, this width is then used to check if the tested feature works as expected.

The next example can be used to test the feature: test_regress/t/t_parameter_type.v
the test can be found at (branch test_sv): https://github.com/jeras/verilator

Regards,
Iztok Jeras
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-04-08T22:08:23Z

Great, merged this into git, though renamed t_param_type to match the other param types.

Closing, as test merged, and feature bug tracked in #�. There's currently a contributor working on param type.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-03-15T01:53:06Z

FYI #� is now resolved, and this test is turned on.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
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