Author Name: Iztok Jeras (@jeras)
Original Redmine Issue: 481 from https://www.veripool.org
Original Date: 2012-04-08

Hi,

The SystemVerilog feature "interface" is not yet supported, I created a test for it. The interface in the example implements a simple handshake protocol (request/grant). The interface connects a request source to a drain which grants the requests. LFSR are used to randomize the request and grant signal. All three (source, interface, drain) count the number of granted requests. The test checks if this three numbers are in agreement before it finishes. Modports are used to prevent the source/drain instances from accessing the interface internal counter.

The next example can be used to test the feature: test_regress/t/t_interface.v
the test can be found at (branch test_sv): https://github.com/jeras/verilator

Regards,
Iztok Jeras