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%Error: ...: Unsupported LHS tristate construct: NOT #495

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veripoolbot opened this issue Apr 26, 2012 · 5 comments
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%Error: ...: Unsupported LHS tristate construct: NOT #495

veripoolbot opened this issue Apr 26, 2012 · 5 comments
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resolution: fixed Closed; fixed

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Author Name: Alex Solomatnikov
Original Redmine Issue: 495 from https://www.veripool.org
Original Date: 2012-04-26
Original Assignee: Wilson Snyder (@wsnyder)


Source code line:

                 .aclr                       (~ctl_reset_n), 

where aclr is declared as:

     input  aclr; 
...
     tri0 aclr; 

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-04-26T11:17:20Z


Should be fixed when #� is.

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Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2012-04-27T01:56:19Z


Still getting the same error on the same line after fix for #�:

%Error: ...: Unsupported LHS tristate construct: NOT

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-04-27T02:00:46Z


Sure you rebuilt? test_regress/t/t_tri_unconn.v has this case, which failed before the fix and not now. Otherwise please make a test case, thanks.

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Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2012-04-27T07:02:37Z


Yes, I rebuilt it twice and this error still occurs.

In your test the wires connected to tri0/tri1 inputs are all constants. So, my guess is that constant propagation removes NOT operation.

In the code the wire connected to tri0 input is not constant.

I modified the test slightly:

module test (/*AUTOARG*/
    // Inputs
    clk
    );
    input clk;

    integer      cyc=0;

    t_tri0 #(.EXPECT(1'b0)) tri0a (.tn(clk));

    t_tri1 #(.EXPECT(1'b0)) tri1c (.tn(~clk));

    // Test loop
    always @ (posedge clk) begin
       cyc <= cyc + 1;
       if (cyc==99) begin
          $write("*-* All Finished *-*\n");
          $finish;
       end
    end

endmodule

module t_tri0
  #(parameter EXPECT=1'b0)
    (tn);
    input tn;  // Illegal to be inout; spec requires net connection to any inout
    tri0  tn;
    wire  clk = test.clk;
//   always @(posedge clk) if (tn !== EXPECT) $stop;
endmodule

module t_tri1
  #(parameter EXPECT=1'b1)
    (tn);
    input tn;
    tri1  tn;
    wire  clk = test.clk;
//   always @(posedge clk) if (tn !== EXPECT) $stop;
endmodule

and got the same error:

verilator -sv --cc -Wno-fatal test.v --top-module test
%Error: test.v:12: Unsupported LHS tristate construct: NOT
%Error: Exiting due to 1 error(s)

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-05-15T18:02:43Z


Bug reporting should have closed this when the duplicate #� closed.

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resolution: fixed Closed; fixed
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